In asynchronous bus isolating/bridging applications, such as a SCSI isolator or bus extender, signals need to be precisely delayed by a predetermined amount in order to guarantee or even improve setup or hold times on the resultant output bus. Current techniques involve the use of a dynamically varying string of standard cells (such as inverters or buffers), of length determined by comparison to a reference delay or clock, to achieve a fixed delay. The delay elements are duplicated throughout the chip. This approach is large, very difficult to test and not very precise.
It is desirable to provide a precise delay circuit that is small. In addition, the delay elements should be tolerant of process, voltage, and temperature variations. The following techniques achieves all these goals.